PICMG Specifications

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Warning! Draft specifications and ECR’s are under the control of the subcommittee, if active. It is PICMG’s policy to prohibit claims of compliance with respect to a specification under development. Any such claims must be understood as applying to a draft, which is subject to change.
PICMG – No.	Name	Revision ECN	Date	Status	Description

COM.0	Computer On Module	R2.1 Errata	7/27/2012	Adopted	COM Express R2.1 Errata
		Rev 2.1	5/14/2012	Adopted	Latest revision including silicon and form factor updates.
		Rev 2.0	8/30/2010	Adopted	Adds additional support for newer chipsets and interfaces.
		R2 Errata 001	10/19/2010	Adopted	COM Express Rev 2.0 - Errata 001
		Rev 1.0	10-Jul-05	Obsolete	Replaced with Rev 2.0
CDG	COM Design Guide	Rev 1.0	4/1/2009	Available	Free interoperability guidelines for COM.0 compliant modules and carriers.
		Rev 2.1	TBD	Active	To match the features added to the COM.0 specification in R2.0 and R2.1 to the Design Guide
3.0	AdvancedTCA® (Base Specification)	Rev 3.0	24-Mar-08	Adopted	Incorporates ECN’s to R2.0 and additional CR’s
		Rev 2.0	18-Mar-05	Obsolete	Replaced by Rev 3.0
		R2 ECN001	15-Jun-05	Obsolete	Adds ShMC Cross Connect. Replaced by Rev 3.0
		R2 ECN002	29-Apr-06	Obsolete	Replaced by Rev 3.0
		Rev 1.0	30-Dec-02	Obsolete	The PICMG 3.0 “core” specification specifies board, backplane and shelf mechanicals; power distribution and the connectivity required for system management. Replaced by Rev 2.0.
		R1 ECN 001	21-Jan-04	Obsolete	Changes incorporated in Rev 2.0
3.1	AdvancedTCA® Ethernet	Rev 2.0	3-Aug-2012	Adopted	Develops enumerated requirements that incorporate 1000BASE-KX, 10GBASE-KX4 and 10GBASE-KR fabric options into Revision 2.0 of the PICMG 3.1 specification.
		Rev 1.0	22-Jan-03	Adopted	Defines how Ethernet and Fibre Channel are mapped onto PICMG 3.0.
3.2	AdvancedTCA® InfiniBand	Rev 1.0	22-Jan-03	Adopted	Defines how InfiniBand transport is mapped onto PICMG 3.0
3.3	AdvancedTCA® StarFabric	Rev 1.0	21-May-03	Adopted	Defines how StarFabric transport is mapped onto PICMG 3.0
3.4	AdvancedTCA® PCI Express	Rev 1.0	21-May-03	Adopted	Defines how PCI Express and PCI Express Advanced Switching transport is mapped onto PICMG 3.0
3.5	AdvancedTCA® Serial RapidIO	Rev 1.0	9/21/2005	Adopted	Defines how Serial Rapid I/O is mapped onto PICMG 3.0
3.6	AdvancedTCA® PRS	Rev 1.0	1/1/0	Abandoned	Defines how Packet Routing Switch (PRS) is mapped onto PICMG 3.0
3.8	AdvancedTCA Rear Transition Module	Rev 1.0	09/05/2011	Adopted	Defines a set of connectors for data and management on the RTM described in PICMG 3.0 R3.0.
3.7	AdvancedTCA® Extension	Rev 1.0	TBD	Active	Develops extensions to AdvancedTCA for use in enterprise applications.
phyTCA	xTCA™ for Physics	Rev 1.0	TBD	Active	Develops additional features and options for AdvancedTCA and MicroTCA for use in particle physics research including data collection and accelerator control systems.
IRTM.0	Intelligent Rear Transition Module	Rev 1.0	1/1/2011	Adopted	Standardizes support for RTMs as manage FRUs.
SFP.0	System Fabric Plane	Rev 1.0	24-Mar-05	Adopted	Defines a consistent method for carrying encapsulated TDM across any AdvancedTCA transport whether it be PICMG 3.1, 3.2, etc. (or a custom transport implementation on PICMG 3.0), as well as for PICMG 2.16.
SFP.1	iTDM	Rev 1.0	24-Mar-05	Adopted	Defines an Internal TDM (I-TDM) multiplexed voice over packet protocol that is optimized for Voice LANs and Packet Backplanes
AMC.0	AdvancedMC™ Mezzanine Module	Rev 2.0	15-Nov-06	Adopted	Defines a mezzanine building block approach for the addition of crucial functionality to a PICMG 3.0 carrier card available from a number of third party suppliers.
		Rev 1.0	1/3/05	Obsolete	Replaced by Rev 2.0
		R1 ECN 001	26-Jun-06	Obsolete	Incorporated in Rev 2.0
		R1 ECN 002	15-Nov-06	Obsolete	Incorporated in Rev 2.0
AMC.1	AdvancedMC™ PCI Express and AS	Rev 2.0	08-Oct-08	Adopted	Defines port usage for PCI Express and Advanced Switching environments on AMC.0
		Rev 1.0	20-Jan-05	Obsolete	Replaced by Rev 2.0
AMC.2	AdvancedMC™ Ethernet	Rev 1.0	1-Jan-05	Adopted	Defines port usage for Ethernet on AMC.0
AMC.3	AdvancedMC™ Storage	Rev 1.0	25-Aug-05	Adopted	Defines port usage for Fibre Channel on AMC.0
AMC.4	AdvancedMC™ Serial RapidIO	Rev 1.0	11-Jul-09	Adopted	Defines port usage for Serial RapidIO on AMC.0
MTCA.0	MicroTCA®	Rev 1.0	6-Jul-06	Adopted	Defines a system architecture that uses AdvancedMC mezzanine cards plugged directly into a backplane without modifications.
MTCA.1	Air Cooled Rugged MicroTCA®	Rev 1.0	19-Mar-09	Adopted	Defines Ruggedized version of MicroTCA for exterior and mobile communications applications.
MTCA.2	Hardened Air Cooled MicroTCA®	Rev 1.0	TBD	Active	Expands the market for MicroTCA into commercial and military ruggedized applications
MTCA.3	Hardened Conduction Cooled MicroTCA®	Rev 1.0	2/24/2011	Adopted	Expands the market for MicroTCA into commercial and military ruggedized applications
MTCA.4	MicroTCA® Enhancements for Rear I/O and Precision Timing	Errata	08/01/2012	Adopted	MicroTCA.4 R1.0 Errata
		Rev 1.0	8/22/2011	Adopted	Defines an AMC and a corresponding MicroRTM module set for rear I/O along with an appropriate MicroTCA shelf.
2.0	CompactPCI®	Rev 3.0	1-Oct-99	Adopted	Incorporates Hot Swap pin sequencing and other enhancements
		R3 ECN 002	23-Jan-02	Adopted	Adds Geographical to Logical Address Mapping to Rev 3.0 Download ECN 002
		R3 ECN001	1-Oct-2008	Abandoned	PCI-X on CompactPCI
		R2.1	2-Sep-97	Obsolete	Defines a IEEE 1101.1 (Eurocard) PCI form factor, and assign a PCI pinout on the IEC 1076-4-101 family of 2 millimeter hard metric connectors. Replaced with Rev 3.0
2.1	Hot Swap	Rev 2.0	17-Jan-01	Adopted	Incorporates ECRs for: Enhanced software connection architecture, 3.3 volt 66 MHz support, PCI-X compatibility, Compliance language
		Rev 1.0	3-Aug-98	Obsolete	Incorporates Hot Swap pin sequencing and other enhancements. Replaced by Rev 2.0
2.2	VME64x	Rev 1.0	9-Sep-98	Adopted	Defines pin assignments for the VME64 Extensions on J5/P4 and J5/P5 of a CompactPCI backplane.
2.3	PMC I/O	Rev 1.0	9-Sep-98	Adopted	Defines user IO pin mappings from IEEE 1386 PMC sites to J3/P3, J4/P4, and J5/P5 on a CompactPCI backplane.
2.4	IP I/O	Rev 1.0	9-Sep-98	Adopted	Defines user IO pin mappings from ANSI/VITA standard IP sites to J3/P3, J4/P4, and J5/P5 on a CompactPCI backplane.
2.5	Telephony	Rev 1.0	3-Apr-98	Adopted	Defines the utilization of pins for the computer telephony functions of TDM bus, telephony rear IO, 48 VDC and ringing distribution.
2.6	Bridging	Rev 1.0	1/1/1	Abandoned	Defines a means for CompactPCI CPU boards to drive two independent PCI bus segments in a 6U environment.
2.7	Dual CompactPCI®	Rev 1.0	11-Apr-01	Adopted	TBD
2.8	PXI	Rev 1.0	1/1/0	Abandoned	Defines a pinout of the J2 connector for use in instrumentation systems based on CompactPCI. (This specification did not pass its membership vote.)
2.9	Management	Rev 1.0	2-Feb-00	Adopted	Defines a secondary system management bus for CompactPCI.
		R1 ECN 001	20-May-02	Adopted	Defines CompactPCI slot connectivity data
2.10	Keying	Rev 1.0	1-Oct-99	Adopted	Defines use of the keying mechanisms defined in IEC 1076-4-101 for the J4/P4 connector and in IEEE 1101.10 for handle and cardguide hardware.
2.11	Power Interface	Rev 1.0	1-Oct-99	Adopted	Defines the electrical and mechanical requirements relating to the functionality and interoperability of plug-in power modules in CompactPCI systems.
2.12	Software Interoperability	Rev 2.0	20-May-02	Adopted	Incorporates ECRs, PICMG 2.1 R2.0,Windows and Linux updates, Redundant System Slot (RSS) API, Switched PCI-PCI bridging support, Hardware- and O/S-independent models of network-connected intelligent nodes, Standards-based management of HS- and RSS-capable CompactPCI platforms and IDSEL to GA mapping.
		Rev 1.0	23-May-00	Obsolete	Defines vendor-independent software interfaces supporting control of the software and hardware connection processes as defined in PICMG 2. Replaced with Rev 2.0.
2.13	Redundant System Slot	Rev 1.0	TBD	Abandoned	Defines an approach to make the PCI System Slot functions redundant so the System Slot CPU can be Hot Swapped.
2.14	Multicomputing	Rev 1.0	5-Sep-01	Adopted	Defines packet-based communications between heterogeneous PCI agents (multi-computing) within the CompactPCI system architecture.
2.15	PTMC	Rev 1.0	11-Apr-01	Adopted	Defines PTMC to support specialized telecom interfaces and coexist with PMC.
		R1 ECN 001	22-Jan-03	Adopted	Enhances TDM capacities by extending the TDM (H.110) bandwidth and adding Ethernet links, as well as combining ATM capabilities with Ethernet links.
2.16	Packet Switched Backplane	Rev 1.0	5-Sep-01	Adopted	Defines a packet based switching architecture on top of CompactPCI.
2.17	StarFabric	Rev 1.0	20-May-02	Adopted	Defines backplane, node card and switch card requirements for StarFabric Protocol.
2.18	RapidIO	Rev 1.0	18-Jun-04	Adopted	Defines redundant, switched, high-speed point-to-point connectivity among some or all slots using Serial RapidIO and coexisting with 64 bit CompactPCI H.110 and optionally PICMG 2.16
2.20	Serial Mesh	Rev 1.0	21-Oct-02	Adopted	Defines a point-to-point serial interconnect intended to add high-speed cell based data transport to the PICMG 2.x platforms.
2.30	CompactPCI® PlusIO	Rev 1.0	11-11-2009	Adopted	Defines the connector, electrical, and mechanical requirements of 3U/6U System Boards, Peripheral Boards, Switch Boards, and Backplanes using PCI Express as peripheral interconnect, and supporting a variety of other switched serial interconnects, with CompactPCI and CompactPCI Express interoperability features.
CPCI-S.0	CompactPCI® Serial	Rev 1.0	3/9/2011	Adopted	This specification adds greater support for serial point to point fabrics like PCIExpress®, SATA, Ethernet and USB in the classic CompactPCI form factor.
2.50	CompactTCA	Rev 1.0	TBD	Abandoned	Defines a set of compatible practices for managed PICMG 2.16 platforms, which constrain implementation options so as to enhance interoperability.
EXP.0	CompactPCI® Express	Rev 1.0	6/27/2005	Adopted	Defined PCI Express in CompactPCI Systems
		Rev 2.0	1/27/2011	In progres	To enable PCI Express Gen 2 (5.0 GT/s) and Gen 3 (8 GT/s) operation in an interoperable multi-vendor fashion.
1.0	PCI/ISA	Rev 2.0	10-Oct-94	Adopted	Defines CPU form factor and backplane connector for PCI-ISA Passive Backplanes
		Rev 3.0	10-Oct-94	Abandoned	Abandoned
1.1	PCI/ISA Bridging	Rev 1.1	25-May-95	Adopted	Defines a form factor and backplane connector layout for PCI-PCI bridge boards
1.2	e-PCI-X	Rev 1.0	23-Jan-02	Adopted	Defines the mechanical and electrical interface to support a standard form factor PCI computer system with either two PCI/PCI-X busses or a single PCI/PCI-X bus and removing ISA bus support.
1.3	SHB Express	Rev 1.0	20-Aug-05	Adopted	Defines PCI Express usage with options for PCI in a classic slot card form factor.
HPM.1	HPMI.1	Rev 1.0	1-Jun-2007	Adopted	Defines management firmware upgrade capability
HPM.2	LAN-Attached IPM Controller	Rev. 1.0	15-Aug-12	Adopted	Standardize LAN-Attached xTCA management controllers
ATCA300	ATCA300	Rev 1.0	TBD	Abandoned	Defines a standard approach for implementing AdvancedTCA in 300mm ANSI and ETSI environments.
RES	Requirements Engineering Subcommittee (RES)	N/A	1-Sep-2007	Complete	This subcommittee is chartered with summarizing and categorizing the mandatory and optional sections of AdvancedTCA and AdvancedMC specifications to make it easier for users and vendors to implement commercial off the shelf systems.
ICC.0	Interconnect Characterization	Rev 1.0	TBD	Active	Specifies methods for the characterization of the passive elements of backplane and mezzanine interconnects.
ASI Core	ASI Core	Rev 1.0	Dec 2003	Adopted	Advanced Switching Core Architecture Specification
ASI PI-8	ASI Protocol Interface #8	Rev 1.0	Feb 2004	Adopted	PCI-Express to Advanced Switching Bridge Architecture Specification
ASI SDT	ASI Socket Data Interface	Rev 1.0	Feb 2004	Adopted	Advanced Switching - Socket Data Interface
ASI SQP	ASI Simple Queuing Protocol	Rev 1.0	Feb 2004	Adopted	Advanced Switching - Simple Queuing Protocol
ASI SLS	ASI – SLS Specification	Rev 1.0	Feb 2004	Adopted	Simple Load/Store (SLS) Specification
ASI Portal	ASI Portal Specification	Rev 1.0	Aug 2004	Adopted	A Standard Interface for Accessing the AS Fabric for PCI Express® Based Systems
		Errata	Mar 2005	Adopted	_
HPM.3	DHCP-Assigned Platform Management Parameters	Rev. 1.0	22-Nov-12	Adopted	Standardize the use of DHCP to assign management controller operational parameters, especially those related to IP addresses

Notes
Completed specifications are those for which at least one revision has been submitted to the Executive Membership and adopted. In a few cases multiple revisions have been completed, resulting in the listing of obsolete revisions.

Completed PICMG® specifications are distributed to all PICMG members as a benefit of membership, and any manufacturer may make claims of compliance. PICMG does not endorse these claims, or assume responsibility for any failure to meet claims of compliance.

Specifications under development are those for which a subcommittee has been, or is in the process of being, formed. In some cases the summary indicates that subsequent revisions of completed specifications are under development. In other cases, where no completed specification is shown the document under development is the first on that subject.

Where available, links are provided from specification descriptions to short form versions of specifications. Short form specifications are provided for information only – do not attempt to design from these documents. The short form documents are subsets of their respective specifications. For complete guidelines on designs and implementations, the full specifications are required.

Warning!

Draft specifications and ECR’s are under the control of the subcommittee, if active. It is PICMG’s policy to prohibit claims of compliance with respect to a specification under development. Any such claims must be understood as applying to a draft, which is subject to change.